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Cadence Delivers Advanced Verification Environment for Palladium Acceleration/Emulation System
New Capabilities Help Speed Time-to-Market and Improve Quality of
First Software and First Silicon for Complex, Multi-Million-Gate SoCs
SAN JOSE, Calif.—(BUSINESS WIRE)—July 15, 2004—
Cadence Design Systems, Inc. (NYSE:CDN) today announced the
availability of an advanced verification environment for the
industry-leading processor-based Incisive(TM) Palladium(R)
acceleration/emulation system. The environment, integrated with the
Incisive functional verification platform, includes new capabilities
that provide the most comprehensive environment for verification of
highly complex, multi-million-gate system-on-chip (SoC) designs.
Capabilities include enhanced transaction-based acceleration
(TBA), verification intellectual property (IP) SpeedBridge(TM)
solutions, further integration with embedded software debuggers, and
additional support for multiple languages and standards -- all
contributing to greater efficiency for meeting first software and
first silicon success.
The Incisive TBA solution, based on the standard co-emulation
modeling interface (SCE-MI), enhances simulation acceleration
performance of the Palladium system by reducing communication between
the testbench running on the workstation and the design under test in
the emulation system. Productivity features include support of
variable-length messages, a faster streaming mode, transaction
recording capabilities and support of both timed and un-timed
testbench components. This solution enables full congruency with the
Incisive unified simulator to shorten bring-up time and assure
reusability of the testbench and the verification IP models.
"This very comprehensive system-level design and verification
methodology encompasses transaction-level abstraction, acceleration
and emulation," said Christopher Tice, senior vice president and
general manager, Verification Acceleration, Cadence. "For simulation
acceleration users, we provide a complete flow that enables reuse of
transaction-level models with high performance. For customers
delivering the most complex SoC designs in the wireless, multimedia
and networking segments, our new vertical solutions improve the
efficiency and ease of verification that the Palladium system already
delivers."
By combining bus interface solutions, software applications,
hardware emulation, real world data connections, and stimulus
generated by external testers into one complete environment, chips or
entire systems can be comprehensively verified earlier in the
development cycle -- shaving months from the verification cycle to
ensure high-quality, first-pass silicon and reliable software.
The new SpeedBridge solutions available now include PCI Express
with support for up to 16 lanes, Multi-Ethernet (10/100, 1GB and 10GB)
with ability to connect into a "live network" or third-party testers,
and Video SpeedBridge enhancements. The USB SpeedBridge solution will
be available during H2 2004. Leveraging Palladium dynamic target
capability, a variety of software debuggers can be connected to the
emulated design, allowing hardware and software integration and debug
flexibility during run time.
"The Cadence PCI Express and RGB SpeedBridges enabled us to
emulate our PCI-Express graphics processor design prior to tape-out,
developing our software simultaneously to the hardware, and
interfacing with the PCI-Express motherboards before our chip was
commercially available," said Michael Shiuan, vice president of
engineering at S3 Graphics, Inc. "The Palladium-based solution is fast
and easy to use, and Cadence backed this up with significant PCI
Express expertise."
Delivering on the Incisive platform vision of multi-language
capability, the environment adds support for Verilog 2001 as a design
language and SystemC/System C Verification library (SCV) as a
testbench language. This enables customers to port their code from
simulation to Palladium with ease and efficiency, compressing overall
verification time. SystemVerilog will also be introduced in phases
starting in H2 2004.
About Cadence
Cadence is the largest supplier of electronic design technologies
and engineering services. Cadence solutions are used to accelerate and
manage the design of semiconductors, computer systems, networking and
telecommunications equipment, consumer electronics, and a variety of
other electronics-based products. With approximately 4,800 employees
and 2003 revenues of approximately $1.1 billion, Cadence has sales
offices, design centers, and research facilities around the world. The
company is headquartered in San Jose, Calif., and traded on the New
York Stock Exchange under the symbol CDN. More information about the
company, its products and services is available at www.cadence.com.
Cadence, the Cadence logo, and Palladium are registered trademarks
of Cadence Design Systems in the United States and other countries.
Incisive and SpeedBridge are trademarks of Cadence Design Systems. All
other trademarks are the property of their respective owners.
Contact:
The Hoffman Agency for Cadence Design Systems, Inc.
Kristin Hehir, 408-975-3098
khehir@hoffman.com
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